This invention pertains in general to merged bipolar and CMOS technology, and more particularly to an isolated high performance vertical PNP transistor and method of producing the same.
In the area of linear circuit design (also known as "analog" circuit design), it has been especially difficult to provide high performance PNP transistors.
CMOS technology is generally a large part of any system. The effort to design large analog systems on a single chip requires front end processes which can provide the needed high performance components. In previous systems, different technologies could be optimized on separate chips. However, when the entire system is integrated on one chip, the processes must be designed such that each technology is optimized.
Heretofore, the PNP transistor technology has often been compromised in order to benefit the NPN and CMOS transistors. The three types of PNP devices commonly used in processes for a merged bipolar and CMOS technology are the lateral PNP transistor, the substrate-PNP transistor, and the vertical PNP transistor with employing either N-epitaxial pocket material or a diffused N-well as the PNP base. They all exhibit a low cut-off frequency due to their wide base regions. These transistors exhibit current gain roll-off at low to moderate current levels, due to the use of lightly-doped base regions. The substrate-PNP is not an isolated device because the collector of each PNP transistor is the substrate. Thus, all substrate-PNP devices on a single chip have a common collector. The lateral PNP device requires a large amount of area in order to build the isolated structure and conduction is often a surface conduction which tends to be noisier and leads to a smaller current carrying capability. The PNP base width in constructions where the base region is a diffused N-well or N-epitaxial pocket material, is dependent upon the thickness of the epitaxial layer and the degree of up-diffusion of a P-buried layer serving as the PNP collector. These base-width determining factors mitigate against a narrow base width.
A PNP transistor has recently been disclosed for integration in a bipolar/CMOS process. That process, however, includes forming a P-type epitaxial layer on a P-type substrate. On the other hand, the processes by which substantially all commercial bipolar/CMOS integrated circuits are now made grow an N-epitaxial layer on a P-type substrate. That represents extensive experience and proven merged techniques for making NPN and CMOS transistors which experience is not possible to use with the PNP transistor in an N-epitaxial layer.
It is therefore an object of this invention to provide a method for making a high performance, isolated vertical PNP transistor in an N-epitaxial pocket.
It is a further object of this invention to make such a PNP transistor in a process wherein, at the most, only few if any masking steps are needed in addition to those already used to form a vertical NPN and a pair of CMOS transistors, all being capable of good performance in analog signal circuits.